Stresses and strains within a feature of an integrated circuit (IC) or an electronic circuit design may cause many undesired adverse effects or even cause the design to fail. Among the many adverse effects, manufacturability, reliability, and performance are of primary concern. For example, the electric stress in the gate oxide caused by the electric field across the oxide has been shown to increase as the voltage drop across the oxide increases; the stress also increases as the temperature rises due to Joule heating which may be further exacerbated due to the introduction of low-k dielectrics because of its higher porosity. The voltage overshoot during device switching further worsens the problem and increases the likelihood of gate oxide premature failure. Moreover, stress induced degradation in electrical parameters may also lead to timing conflicts in digital circuits and mismatch in analog applications, and such stresses may also cause noise due to the accelerated dielectric deterioration and eventual breakdown.
In the deep-submicron technologies, the continual push for increased carrier mobility and decreased resistance and capacitance demands thinner gate oxides (especially for high performance ICs) and thinner silicon (Si) film thickness further exacerbates the problem. Deep-submicron technologies often employ thin gate oxides in order to reduce capacitance and thus to improve timing. For example, at 65 nm technology nodes, the nominal gate oxide thickness is about 1.2 nm. On the other hand, thinner gate oxide layer increases the oxide tunneling leakage current. It has been shown that the oxide tunneling leakage current increases roughly two and half times for every 0.1 nm reduction in oxide thickness. Current semiconductor fabrication techniques use nitrided oxide to reduce leakage by an order of magnitude. However, the oxide tunneling leakage current has been shown to be as great as 100 A/cm2 for 1.0 nm thick nitrided oxides or even 1000 A/cm2 without nitridation while the design criterion is usually no higher than 1.0 A/cm2. This leakage current poses a great challenge to controlling the thickness of the gate oxide as well as the design.
Moreover, thinner silicon films have shown to improve performance by reducing junction capacitance, but such films also cause the body resistance to degrade and worsens Joule heating and thus may render the design feature less effective or even useless.
In the area of routing, one of the crucial factors is the total number of vias connecting various metal layers, the line lengths and widths, and the overlap of metal lines around the vias. It is known that the cathode vias usually exhibit tensile stresses and the anode vias usually compressive. The tensile stresses may cause stress-induced void nucleation and growth and therefore increase resistance and thus Joule heating which further worsens the electro-migration due to higher metal-ion diffusion and the stress state of the vias. Moreover, whether the feature is subject to DC, pulse-DC, or AC and the direction of the current flow are among the more important criteria in via placement. As such, one of the design goals is to avoid having a single via carry high DC current, particularly in the downstream direction (current flow from the upper metal layer to the lower metal layer.) Furthermore, the mechanical stress caused by thermal expansion mismatch among different materials within the stack or by other processing steps can also cause reliability or manufacturability problems in the vias. One method to address this via placement is to add redundant vias. This method may provide somewhat satisfactory solutions for current technologies, but it fails to address the root cause of the problem which is the tensile stress within the features.
Furthermore, certain processing techniques and materials may contribute to the in-film stresses due to the intrinsic material properties, individual process characteristics, and/or inherent process variations. For example, various plasma enhanced deposition processes may cause electric stresses (plasma-induced damage) that may consume the life of the gate oxides or cause drifts in the MOSFET parameters. Also, certain deposited films, such as tantalum nitride, exhibit tensile stress during and after fabrication while tantalum films exhibit compressive stresses. Moreover, for copper damascene processes, it has been shown that the time between chemical-mechanical polishing (CMP) and dielectric deposition on copper also adversely affects the dielectric strength of the material. The development of chemical-mechanical polishing (CMP) has become important for multilevel interconnection because it is the only technology that allows global planarization. In chemical-mechanical polishing, it has been shown that the flow stress of the copper film increases with the copper film thickness after the CMP planarization process.
On the other hand, the film stress state also affects fabrication processes. For example, results from oxide CMP experiments suggest that the wafer curvature results in a non-uniform polish rate distribution across the wafer. This stress-dependent polish non-uniformity is attributed to the non-uniform pressure distribution across the wafer, induced by the wafer radius of curvature which results from film stresses. Furthermore, it was found that the magnitude of oxide film stress itself has little effect on removal rate. Oxides with tensile stress tend to have a weakened bond structure and enhanced chemical reactivity, both of which result in slightly higher removal rates. The reverse is also true for oxides with compressive stress. Deviations from the model prediction may result from the stress induced by slurry flow, local variations in wafer shape and form, and pad surface properties.
Conventional approaches in stress or strain analysis measure the distances from the both trench isolation edges to poly-Silicon and then use this measurement to estimate the effects of stress. This may be done in two ways. One conventional approach picks the SPICE model based on the distance of the poly from the edge of the active area. The other approach allows extract to find the distance from the trench isolation edge and then adds this distance as a parameter to the SPICE model, which then estimates the effect on the transistor. However, these conventional approaches merely approximate the expected stresses but not the actual stresses. Furthermore, conventional approaches also do not take into consideration other sources of stresses such as other layers or neighboring devices.